(1) Field of the Invention
The present invention relates to methods employed to fabricate semiconductor devices, and more specifically to a method used for fabrication of a complementary metal oxide semiconductor (CMOS) device, using strained layers for the channel regions of the N channel metal oxide semiconductor (NMOS) device, and for the P channel metal oxide semiconductor (PMOS) device.
(2) Description of Prior Art
Strain induced band structure modification and mobility enhancement, used to increase drive current, can be an attractive feature if implemented for CMOS devices. Enhanced electron mobility in silicon under biaxial tensile strain, and enhanced hole mobility in silicon-germanium (SiGe), under biaxial compressive strain, if properly integrated in CMOS fabrication sequence would enhance the performance for both the NMOS and PMOS devices. This invention will describe a novel process sequence in which stacked layer structures, one comprised of thin silicon on SiGe, and the other comprised of thicker silicon on SiGe, provide the channel region under biaxial tensile strain needed for NMOS performance enhancement, as well the channel region under biaxial compressive strain needed for PMOS performance enhancement. Prior art, such as Chu et al, in U.S. Pat. No. 5,906,951, Leoues et al, in U.S. Pat. No. 5,659,187, Kawakubo et al, in U.S. Pat. No. 6,165,837, Fitzgerald et al, in U.S. Pat. No. 6,291,321, Solomon et al, in U.S. Pat. No. 5,019,882, and Murakami et al, in U.S. Pat. No. 5,241,197, offer procedures for forming strained layers on insulator. However these prior arts do not describe the novelty of this present invention in which a fabrication sequence for an NMOS channel region under biaxial tensile stress, and a PMOS channel region under biaxial compressive stress, allows formation of these desired channel regions on the same semiconductor substrate allowing CMOS performance enhancement to be realized.